Integrated circuits are fabricated by a series of batch processes in which wafers, typically of silicon or other compatible material, are processed to produce a particular type of integrated circuit. Each wafer contains a plurality of integrated circuits or chips, typically of the same kind. As is known, chemical, thermal, photolithographic and mechanical operations are typically involved in the fabrication of the integrated circuit wafer. Because of variations across the wafer and across each individual chip caused by process variables or physical phenomena, however, not all chips on the wafer will meet the desired specifications for the chips. Some method of testing must be employed to determine which chips on any given wafer meet the specifications.
Integrated circuit chips are typically fabricated with one or more layers of metal interconnect on the surface of the chip which provide connecting paths to form the desired circuit. The metal interconnect layer or layers also provide a means to make connections to the integrated circuit chip when the chip is separated from the wafer and is assembled into a package or carrier. Interconnect points, typically called "bonding pads", are formed by the metal interconnect and are arrayed on the surface of the chip so as to allow small bonding wires or other connecting means to be connected from the integrated circuit chip to its carrier or package. These same bonding pads, and others designed specifically for test purposes, are used to make electrical contact to each individual chip for testing the electrical characteristics of the chips even while still joined together in wafer form.
The yield of good chips on a wafer is defined as the percentage of good dies with respect to the total dies present on the wafer. Yield is the single most important cost factor in the production of integrated circuit devices. Each process and test step may be considered a potential yield loss point. The testing of each die on the wafer may result in yield loss not only from improper earlier processes, but also from problems which can occur due to errors in testing operations. For example, during a probe testing operation electrical contact must be made to the bonding pads of each integrated circuit in order to stimulate electrically the circuit and to measure critical parameters. An array of fine wire probes, conductive bumps and/or free beams formed on a card is aligned so as to correspond with the array of bonding pads and is used to contact mechanically and electrically the array of bonding pads. Typically, each die on the wafer is sequentially positioned and aligned under the array of probes, for example, and the wafer is moved up to allow contact of the respective probes onto the chip. Precision wafer movement stages allow each chip to be positioned under the probe array, brought into contact with the probe array, and tested. The chips on the wafer which do not pass the electrical test are marked by some method such as by applying a dot of ink or by storing their respective position on the wafer in computer memory for later recall.
In most cases, the interconnecting metal layer or layers of the integrated circuit chip are formed of aluminum or sometimes gold. These metals provide good processing characteristics and good electrical characteristics. However, these metals are also rather soft in comparison with the typical materials used for forming the probes on the card (referred to herein as an integrated circuit probe card). As a result, it is likely that damage to the bonding pad area will occur if the probe card is not properly constructed, aligned, adjusted and utilized. For example, the tips of the probes must be carefully adjusted for planarity to insure that all probes touch the respective bonding pads at relatively the same time. The probes must also be adjusted to contact, e.g., touch down, accurately on each pad. After the probes initially contact the respective bonding pads, a proper amount of overdrive must be maintained past the point of initial contact in order to provide a contacting force resulting in a consistent low resistance contact. The tips of the probes themselves must be capable of providing low resistance contact between the probe and the bonding pads and should be free of contaminants which prevent good electrical contact. The contacting force or spring constant of the probe itself is also a parameter which must be considered in determining the ability of a probe to provide a proper contact.
Various technologies have been used to produce probe cards for testing integrated circuits. The most common types are blade, epoxy ring and membrane technologies. A fourth type, which involves what is referred to a "buckling beam", also has been used by some manufacturers. Blade technology is discussed in U.S. Pat. No. 4,161,692 for a "Probe Device for Integrated Circuit Wafers"; U.S. Pat. No. 3,849,728 for a "Fixed Point Probe Card and an Assembly and Repair Fixture Therefor"; and U.S. Pat. No. 4,382,228 for a "Probes for Fixed Point Probe Cards". Epoxy ring technology is discussed in U.S. Pat. No. 3,835,381 for a "Probe Card Including a Multiplicity of Probe Contacts and Methods of Making"; U.S. Pat. No. 3,905,008 for a "Microelectronic Test Probe Card Including a Multiplicity of Probe Contacts and Method of Making Same"; U,.S. Pat. No. 4,599,559 for "Test Probe Assembly for IC Chips"; and U.S. Pat. No. 4,757,256 for a "High Density Probe Card". Buckling beam technology is discussed in U.S. Pat. No. 4,554,506 for a "Modular Test Probe"; and U.S. Pat. No. 4,843,315 for a "Contact Probe Arrangement for Electrically Connecting a Test System to the Contact Pads of a Device to be Tested".
The most commonly used type of technology to produce integrated circuit probe cards is epoxy ring technology, although the other technologies are similar. In the construction of an epoxy ring type probe card, a sheet of mylar is punched or drilled with a series of holes in the same array pattern as the bonding pad locations on the chip. The holes are sized to accept the tip of each probe and hold the tip in position during construction of the card. These holes are typically 0.001 inch to 0.002 inch in diameter. Each probe is made from a length of spring wire which is tapered to a point at one end and bent down at a steep angle to form a probe tip. Each probe tip is placed in a corresponding hole in the mylar sheet. The other end of each spring wire probe is arrayed in a generally circular pattern with those of the other probes and is secured in place by a ring of epoxy or another suitable material. The ends protrude through the epoxy in order to be soldered to a circuit board which forms the probe card. After the probes are soldered to the circuit board, the probe tips are sanded to provide relatively flat probe tips positioned in a relatively planar array.
Various systems have been used to inspect the probe cards and, for example, to adjust the probe cards. The critical parameters for probe cards include planarity of the probe tips, contact resistance, electrical leakage from probe to probe and alignment of the probe tips relative to the bonding pads. Other important parameters are probe tip diameter, contact force or spring constant of the probe, and the length of the probe tip. Failure of the probe card to meet the required parameters can result in errors when using the probe card to evaluate chips on a wafer.
Methods for measuring planarity, contact resistance and leakage are known in the art. Alignment of the probe tips has typically been evaluated by way of a visual comparison of the probes to the bonding pad array of the integrated circuit, and more recently, by way of an electrical method described in U.S. Pat. No. 4,918,374 entitled "Method and Apparatus for Inspecting Integrated Circuit Probe Cards" and in U.S. Pat. No. 5,060,371 entitled "Method of Making Probe Cards". The measurement of probe tip diameter, contact force and the length of the probe tips has typically been performed using known manual methods.
Determining the planarity of the array of probe tips is typically accomplished using a flat metal plate held parallel to the surface of the probe card. The probes are then sequentially scanned to determine when contact occurs with the metal plate as the plate is incrementally moved along a Z-axis so as to be brought into contact with the probes. As each probe makes contact, the position of the plate with respect to the surface of the probe card is recorded. Thus, the Z-axis positions of all the probe tips are determined. However, conventional probe card inspection systems offer very little in the way of assistance to the operator for adjusting the heights of the probes to form a more planar array. Moreover, if two or more probes in an array are parallel connected or "bussed" to allow extended current carrying capacity, additional tests must be performed to determine their individual Z-axis positions. A method of isolating individual probes is required to determine when each probe touches the conducting surface. A variety of pins, insulators with holes and conducting dots with surrounding insulator material have been used for this purpose.
Contact resistance of the probe tips can be measured using conventional techniques for the measurement of low resistances. A typical method would be to bring the probe tip into contact with a conducting metal surface and measure the resistance of the resulting interface. After probes are in contact with the contacting metal surface, current is forced, via the multiplexer interface, on each probe and then the subsequent voltage of each probe is measured. The measurement preferably is performed at a known deflection or "overdrive" of the probe after the initial contact with the surface. Since the resistances are typically very small, e.g., on the order of a few tenths of an Ohm, Kelvin measurement techniques are required for accurate measurements. The type of metal used for the contact plate is typically gold and some differences will be observed between the resistance measured by these conventional methods and the actual resistance observed when the probe is contacting bonding pads formed using aluminum metalization, for example, on the integrated circuit chip.
Furthermore, since the aluminum is rather soft in comparison with the probe tip material, the tip of the probe will tend to protrude or "dig" into the aluminum and make contact over a much larger surface area of the tip as compared to on the harder gold surface. The angle of the probe tip relative to the bonding pad is such that a scrubbing motion is created when the tip is driven against the pad. In the case of a bonding pad made of soft aluminum, this creates a scrub mark corresponding to the path of the probe tip on the pad. Accordingly, it will be appreciated that the more that is known about the size and shape of the probe tips and the scrub marks they create, the more complete the understanding of the ability of the probe tip to maintain low contact resistance.
Electrical leakage between probes on the probe card may adversely affect the testing of the integrated circuit. Therefore, it is important to inspect for electrical leakage. Leakage may be measured by applying a potential to each probe in sequence and grounding the remaining other probes, and then measuring the current which flows. However, the test must take into account any bussed probes or components such as resistors, diodes and capacitors which may be permanently connected to the probes and form a part of the probe card. In order to perform a complete inspection of the probe card for electrical leakage, it is necessary to check each probe relative to every other probe to ensure there are no leakage paths.
Conventional inspection systems do not distinguish which tests in a series of different tests should be performed first on the probe card. However, in order to properly test for planarity it is desirable to test first for leakage to avoid incorrect results from probes which have excessive leakage.
The X,Y locations of the probes (corresponding to an X-axis and Y-axis) with respect to the bonding pad locations on the integrated circuit have typically been adjusted using manual means and comparing the X,Y locations to an actual integrated circuit chip or a film representation thereof. The probes, or the scrub marks on the pads, provide the visual comparison for the operator to determine which direction to bend or reposition the probes in order to achieve proper alignment. This alignment task becomes increasingly difficult and prone to operator error with high numbers of probes in a given array. The electrical method disclosed in U.S. Pat. Nos. 4,919,374 and 5,060,371 determines the X,Y positions of the probes by determining the contact point of each probe on orthogonal conducting strips on an insulating material. This technique is only suitable for coarse approximations, however, as the flat shape of each probe tip causes actual the contact point between the probe tip and the conducting strips to be offset from the center of the probe tip. This results in measurement errors which are proportional to the diameter of the probe or the distance thereacross if shaped other than a circle. Also, the technique requires that the probes be brought into contact with the insulating material and conducting strips a very large number of times in order to determine the X,Y positions of all the probes. This can result in excessive wear on the probe tips. For example, because the insulating material is typically ceramic, the probe tips may be abraded excessively and pick up contaminants from the rough ceramic surface.
In view of the aforementioned shortcomings associated with conventional probe card inspection systems, it is desirable to have an inspection system which tests the X,Y locations of the probes on the probe card without requiring an actual wafer or a film representation of the bonding pads. The design information of the pad locations and sizes is typically available in computer readable form before the photomasks or the wafers are produced. It is desirable to import this information directly into the inspection system performing the X,Y location test to avoid errors and to be able to produce a probe card even before wafers are available. It is also desirable that the inspection system be able to determine automatically the proper probe locations and configurations from the photomask used to create pad openings in the protective glass layer over the chip. In addition, it is desirable that the inspection system be able to use a known good probe card for the same purpose when other means are not available.